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PE4302
Product Specification
Figure 14. Pin Configuration (Top View)
Table 3. Absolute Maximum Ratings
Symbol
V DD
V I
Parameter/Conditions
Power supply voltage
Voltage on any DC input
Min
-0.3
-0.3
Max
4.0
V DD +
0.3
Units
V
V
C16
1
15
C8
T ST
Storage temperature range
-65
150
°C
RF1
Data
Clock
2
3
4
20-lead QFN
4x4mm
Exposed Solder Pad
14
13
12
RF2
P/S
Vss/GND
P IN
V ESD
Input power (50 ? )
ESD voltage (Human Body
Model)
+30
500
dBm
V
LE
5
11
GND
Exceeding absolute maximum ratings may cause per-
manent damage. Operation should be restricted to the
limits in the Operating Ranges table. Operation be-
tween operating range maximum and absolute maxi-
mum for extended periods may reduce reliability.
Table 2. Pin Descriptions
Table 4. Operating Ranges
Pin
No.
1
2
Pin
Name
C16
RF1
Description
Attenuation control bit, 16dB (Note 4).
RF port (Note 1).
Parameter
V DD Power Supply
Voltage
I DD Power Supply
Current
Min
2.7
Typ
3.0
Max
3.3
100
Units
V
μ A
3
4
5
Data
Clock
LE
Serial interface data input (Note 4).
Serial interface clock input.
Latch Enable input (Note 2).
Digital Input High
Digital Input Low
Digital Input Leakage
0.7xV DD
0.3xV DD
1
V
V
μ A
6
V DD
Power supply pin.
7
PUP1
Power-up selection bit, MSB.
Input Power
+24
dBm
8
PUP2
Power-up selection bit, LSB.
Temperature range
-40
85
°C
9
10
11
12
13
14
15
16
17
18
19
20
Paddle
V DD
GND
GND
V ss /GND
P/S
RF2
C8
C4
C2
GND
C1
C0.5
GND
Power supply pin.
Ground connection.
Ground connection.
Negative supply voltage or GND
connection(Note 3)
Parallel/Serial mode select.
RF port (Note 1).
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Attenuation control bit, 1 dB.
Attenuation control bit, 0.5 dB.
Ground for proper operation
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS? device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS? de-
vices are immune to latch-up.
Switching Frequency
The PE4302 has a maximum 25 kHz switching rate.
Note 1: Both RF ports must be held at 0 V DC or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 k ? resistor to V DD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V SS (-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 k ? resistor in series, as close to pin as possible to
avoid frequency resonance.
Document No. 70-0056-04 │ www.psemi.com
Resistor on Pin 1 & 3
A 10 k ? resistor on the inputs to Pin 1 & 3 (see Figure
16) will eliminate package resonance between the RF
input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
?2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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